tytower wrote:You have been proved wrong on GPIO2 but won't admit it .
Please, give us the quote here !!!
(because I don't have to admit anything, the engineering facts are there : https://github.com/esp8266/esp8266-wiki ... ot-Process)
- GPIO0 is pulled up by R2 when the adapter is disconnected, and driven by the adapter's active low DTR signal when connected, which enables the UART download mode when low, and normal Flash boot up when high.
- GPIO2 is pulled up internally, however, as @martinayotte said, I would strongly recommend adding an external 10k pullup resistor on GPIO2, as you will get a much better noise margin than with the internal weak pullup resistor and thus be less sensitive to garbage on this signal. Every serious ESP8266 board is doing this, for good reasons (NodeMCU v0.9, NodeMCU v1.0, Huzzah). Leaving such an critical pin unconnected is calling for troubles: it may work in the lab, but will fail in real world situations when you get a strong electromagnetic field (such as thunderstorm) or ESD
Also, make sure your power supply is able to handle the peak current of 250 mA, I would recommend doubling this figure just to be safe.
Having almost 35 years of electronical/software engineering experience, I'm usually voting for safe bet.
But in case of ESPs, my experience changed a lot, I'm now even playing strong safety !
Let's just imaginate an ESP devices in the fields with harsh environment which his doing deep-sleep for a certain amount of time, and then it wake-up exactly at the moment when ESD is stronger than the weak internal pullups and driving the GPIO0 or GPIO2 to a level equivalent to LOW (yes, ESD is AC, so it can act an LOW or as HIGH depending of it waves), the ESP will simply wake-up in a bad mode, device been stucked there forever until you recycle the power to make it run again.
Now, why having those external pullups even if there are some internal ones ? Simply because those internal ones are too weak ! Maybe Expressif should have choosen stronger ones.
Just to prove that, their document 0B-ESP8266__Hardware_User_Guide__EN_v1.1.pdf (http://bbs.espressif.com/download/file.php?id=562) has a contradiction (which seems to admit the above facts) :
In the Section "2.2.2 Power-on Sequence and Power Reset", they mentioned "There is an internal pull-up in the CHIP_EN pin, so no external pull-up is needed." and few lines later "If voltage for CH_EN pin is low, the chipset ESP8266EX will power off. Note that this pin cannot be dangled.".
So, this means they admit that an external strong pullup is NOT superfluous ...
Also, in the same section, they mentioned "There exists internal pull-up resistor in the reset pin, Pin32, which can be left dangled when it is not used. When the chip is enabled, the reset pin is held low. In order to avoid reset caused by external interference, the lead is generally required to be short, and no external pull-up resistor is necessary.".
We all remember that many people on the forum have posted thread about this reset issue due to "antenna effect", but here, in this case, Espressif never updated their specs specifying not to leave the pin dangled, but maybe they will in the future.
All this is true with ANY critical pins, even if GPIO0/GPIO2 is read only during few nanoseconds, the "antenna" effect still can lead to improper state.
The conclusion is that I've always said that since the beginning, member "Cal" stated more than 6 weeks ago that I was right because he understand what is the "antenna" effect, and I'm pretty sure there are several other members who already agree but they did not given their voice yet here.