ESP8266 Community Forum

Hi,

I have a sensor that communicates with a Double Data Rate (DDR) SPI protocol, where bits are transmitted on a single MISO line on both the rising and falling edge of the clock signal. Does the ESP8266 support this type of communication? I don't see any registers to control this in the technical reference, but some registers are undocumented. Hopefully it's just hiding somewhere

Thanks!

For completeness, I did not find any hidden double data rate (DDR) capabilities in the ESP. However, I was able to communicate with a sensor that returned MISO data using a DDR protocol with some magic:

1) Run the ESP8266 clock at twice the speed required by the slave

2) Input the clock line from the ESP to a divide by 2 counter (I used a D-type flip flop).

3) Connect the slave to the divided clock from the flip flop, and regular miso, mosi and chip select lines from the ESP8266.

4) When transferring to and receiving from the slave, the ESP should use twice as many bits. For instance, if the slave expects an 8 bit MOSI command (10000000), deliver a 16-bit "doubled up" command (11000000 00000000). From the slave's perspective, this is a regular 8 bit command, because the clock is running at half the speed.

5) Because the slave is using a double data rate protocol, any data returned on the MISO line from the slave's perspective will have a bit on the upward clock edge, as well as on the downward clock edge. From the ESP perspective, every bit is simply from an upward clock edge of the faster clock due to the divide-by-2 counter.

This appears to work pretty well, and because the ESP's clock runs so fast, it can support 40MHz DDR devices. Hopefully this helps anyone in the same boat as me.

References:

How to "double-up" commands for mosi line
https://stackoverflow.com/questions/490 ... rse-morton

Divide by 2 counter using flip-flops
https://www.eecs.tufts.edu/~dsculley/tu ... lops5.html

Double-data rate description:
https://en.wikipedia.org/wiki/Double_data_rate