- Fri Aug 13, 2021 6:37 am
#92061
Has anybody also wondered about the rom_i2c_* functions?
My thoughts:
- there is inside the die "hidden" a real I2C hardware module that is used to drive a.o. the PLL (where the functions are used for). This would be interesting, because there is a slight chance the hardware module could have it's I/O's routed to external GPIO's using the I/O mux. Not very likely though, because I've never seen an I2C driven PLL and it would make no sense within a die.
- they're actually a misnomer and should read "rom_i2s_*" which is more probable than thought #1. But then, why call it "i2c/i2s" as it drives the PLL subsystem, not only for I2S. On the other hand, the reasonings by Espressif have been puzzling before (understatement...)
In the end it would be nice to know all the ins and outs of the PLL/clock divider subsystem altogether, either with knowledge of the meaning of the parameters to these functions or even better, on hardware register level. It appears the ESP8266 can run quite a bit faster than 160 Mhz, probably without wifi support, but then we'll shut that down for a moment, run fast, re-enable it and go back to 160 or 80 MHz.
Having said that, I can't see any difference in power use between 80 and 160 MHz, so it's probably not useful to run it on the default 80 MHz at all.
My thoughts:
- there is inside the die "hidden" a real I2C hardware module that is used to drive a.o. the PLL (where the functions are used for). This would be interesting, because there is a slight chance the hardware module could have it's I/O's routed to external GPIO's using the I/O mux. Not very likely though, because I've never seen an I2C driven PLL and it would make no sense within a die.
- they're actually a misnomer and should read "rom_i2s_*" which is more probable than thought #1. But then, why call it "i2c/i2s" as it drives the PLL subsystem, not only for I2S. On the other hand, the reasonings by Espressif have been puzzling before (understatement...)
In the end it would be nice to know all the ins and outs of the PLL/clock divider subsystem altogether, either with knowledge of the meaning of the parameters to these functions or even better, on hardware register level. It appears the ESP8266 can run quite a bit faster than 160 Mhz, probably without wifi support, but then we'll shut that down for a moment, run fast, re-enable it and go back to 160 or 80 MHz.
Having said that, I can't see any difference in power use between 80 and 160 MHz, so it's probably not useful to run it on the default 80 MHz at all.
