ESP8266 Community Forum

- Wed Sep 08, 2021 12:32 pm #92261 Looks like this is the setting that doubles the CPU clock.

Code: Select allDPORT_BASEADDR[0x14/4] |= 0x01; //Overclock bit.

- Wed Sep 08, 2021 12:54 pm #92262

Looks like this is the setting that doubles the CPU clock.

Code: Select allDPORT_BASEADDR[0x14/4] |= 0x01; //Overclock bit.

Yhea, but i didnt find nothing about that, maybe there is something in the docs that you have?

- Wed Sep 08, 2021 6:30 pm #92264 I FIND SOMETHING!!! I map all possible CPU clocks, with this code:

Code: Select all   uint32_t i = 0;
   for (i = 0; i <= 0xff; i++) {
      rom_i2c_writeReg(103, 4, 2, i);
      int j = 0;
      for (j = 0; j < 5; j++) {
         int j = 0;
         for (j = 0; j < 200; j++) {
            uart_div_modify(0, (j * 1000000) / 115200);
            printf("cpuworkingreg: 0x%x, pllworkingfreq: %d \n", i, j);
         }
      }
      call_delay_us(100000);
   }

i call it on nosdk8266.c, on the part when we select a frequency, the highest that i found was 0x2c/0x2d/0x2f/0x44/0x45/0x46/0x61/0x80, that value on the CPU register means 390 MHz of core clock!!!! and 195 MHz of PLL. I used this code to try it:

Code: Select alluart_div_modify(0, (184 * 1000000) / 115200);
    while (1) {
       printf("CPU+PLL working!\n");
    }

and in the frequency selector place it was printing! but on the main.c no. After some debugging, i found that the

Code: Select allCache_Read_Enable

on nosdk8266.c and all the cache code on main.c was generating problems! why? idk, but if you comment the Cache_Read_Enable on nosdk8266_init on nosdk8266.c and you turn off the test that is done in main.c.

I also found that here https://github.com/cnlohr/nosdk8266/blob/master/src/nosdk8266.c#L44 Charles says that you cant link 0x0, well, if you remove all references to cache you can link it!! I still working with some inestability issues, we have a lot of possible registers for set the PLL at 184, and 8 registers to set the CPU at the highest frequency, so sometimes, after some minutes of perfect work, you have a fatal exeption (28) or something, now im running a full scann of everything, this new code try every possible CPU register with every existing PLL register, im expecting a .txt of arround 1 GB . But if we find the perfect formula, we have the 40c ESP8266 running and having UART connection at ~400 MHz!!!!!

- Thu Sep 09, 2021 9:52 am #92277 I am very curious of your findings.

Do you do anything with the "cpu clock doubler" (i.e. turn it off or on explicitly)? I'd rather have a CPU running at a "high" frequency and the APB at half of it (like it normally does), because then there is more chance that all peripherals will continue to work.

The CacheReadEnable (-Disable) functions have to do with mapping flash memory to IRAM. I am not sure how your knowledge is at this point, forgive me if you already know: there is in total 64 kb IRAM in the ESP8266. 32 kb is used for "iram" code i.e. functions that are not specifically mentioned as to not cache in IRAM. The other 32 kb is used for caching flash memory as the processor cannot execute instructions directly from flash. The CacheReadEnable functions (or CacheReadEnable2 versions) set up this caching. They can "mirror" at most 1 Mbyte of flash memory and you can choose which one, out of four (@ 0 Mb, @ 1 Mb, @ 2 Mb, @ 3 Mb).

I think your code runs in IRAM (I don't know how you build it to an image?), so it shouldn't depend on the flash cache. I don't know why the nonosdsk does something with it anyway?