ESP8266 Community Forum

- Sun Jun 26, 2016 3:57 pm #49830 Hi,

I would like an ESP8266 (ESP-12F module) to spy on a (unidirectional) SPI connection, so the ESP has to behave as a SPI slave.
I read some people (namely David Ogilvy http://d.av.id.au/blog/tag/hspi/ ) have had success using the HSPI interface, but as far as I can tell it's oriented towards SPI master functionality.
Any idea if SPI slave has already been done on this chip in the Arduino environment ?

Kind regards,

Vicne

Last edited by Vicne on Thu Jun 30, 2016 3:45 am, edited 1 time in total.

- Tue Jun 28, 2016 5:24 pm #49933 Hi, all,

I now have a sketch working perfectly on Arduino Uno but I'm still not sure how to port it to ESP8266.

I see two ways, but I would like to hear your opinions or tips on the subject :

1) using hardware SPI:
I see source files (e.g. hardware\esp8266\2.2.0\cores\esp8266\esp8266_peri.h ) reference both SPI0 registers (with the comment "SPI0 is used for the flash") and SPI1 registers (without any comment). Does the ESP8266 have a second SPI bus available ? Is it what is called HSPI in other documents ? Can I use it along with SPI0 ? Can it work in slave mode ? What are the pins associated to it ?

2) using software SPI:
I am thinking of using two interrupts, one on the Chip Select pin and one on the CLK pin, but timing will be key. The signal I have to read is clocked at 250kbps, so as the ESP8266 runs at 80MHz (or respectively 160MHz in hi-speed), I should process 1 interrupt every 320 (resp 640) CPUclock cycles. The handler would just sample the MOSI input, shift it in a byte, and push that byte in a queue every 8 clock cycles, so this is probably doable pretty quickly (in assembly if needed), but as the CLK edge occurs right at the middle of the bit, I cannot afford a delay of more than 160 (resp 320) CPU clock cycles between the CLK edge and the sampling of the value (if it's too tight, I could almost double that by triggering on the opposite edge, letting a few cycles go, and then sampling to target the "beginning" of the bit, even before the "official edge" occurs, leaving more margin for the edge-handler delay).
Do you think it is realistic to have such short notices for interrupt handling ?

Note: data on the SPI bus is repeated regularly and I can check its format for validity, so I could afford to miss one bit every now and then, but not more than, say, 1-2%

Any comment would be greatly appreciated.

Kind regards,


Vicne

- Thu Jun 30, 2016 3:44 am #49986 Hi,

No code progress yet, but I discovered I had overlooked the details in the esp8266_peri.h file, and it contains in fact lots of information regarding Slave functionality, including the full description of dedicated registers but Google does not find any page using "SPI1S" "SPISE" and such, so this area seems rather unexplored to say the least.
I'm going to continue investigating the "hardware SPI" track, and I'll report progress (if any) here.

In the meantime, please don't hesitate to post any information or comments.
For example, could anyone confirm that SPI1 is another name for HSPI ?

Kind regards,

Vicne

Last edited by Vicne on Sat Jul 02, 2016 5:08 pm, edited 1 time in total.

- Thu Jun 30, 2016 7:09 pm #50011 Let me make your life easier
The following two URLs contain some old code I have written long time ago and is laying around. One is a C version of SPI slave and the other is the sketch to run on the master device. There are 4 callbacks that the ESP slave needs to attach to in order to get the events when particular event happens. Two are read/write of the 32 byte scratch (the data registers in SPI) and the other two read/write to a 32 bit special SPI Slave status register.
I will wrap this in a nice lib soon, but here is the raw stuff for you to give a shot at:
ESP SPI Slave C
ESP SPI Master
some includes are missing from the C code, but you will figure it out

Async HTTP and WebSocket Server for ESP8266
Async TCP Library for ESP8266
ESP8266 Exception Stack Trace Decoder