Wire Library / Hold SCL low (clock stretching)
Posted: Wed Oct 12, 2016 4:28 amHi all
I wonder how to handle the situation when a slave holds down SCL (clock stretching) when it's busy. In my case it is a MAX11645 ADC that starts a conversion after receiving the eighth’s address bit and the holds down SCL until conversion finished and data ready to be read.
I don’t know how I have to handle this with the wire library.
Any inputs most welcome.
Best regards
Thomas
OK, I found it.....
I wonder how to handle the situation when a slave holds down SCL (clock stretching) when it's busy. In my case it is a MAX11645 ADC that starts a conversion after receiving the eighth’s address bit and the holds down SCL until conversion finished and data ready to be read.
I don’t know how I have to handle this with the wire library.
Any inputs most welcome.
Best regards
Thomas
OK, I found it.....