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How to single step cpu in xtos sdk using icount?

PostPosted: Thu Jun 11, 2015 12:31 am
by cal
Dear ESP8266 hackers,

I want to implement better debugger single stepping on the esp8266.
I am able to use the icount/icountlevel registers for that to debug user level tasks at intlevel 0.
My problem is that the intlevel1 handler executes some code at intlevel 0, too.

That leads to the following:
The debugger stopped at some user level code.
I do an assembler level single step that is translated into icount.
An int1 interrupt occurs and as soon as the int1 handler lowers its intlevel the debugger stops one instruction
later.
We end up in the int handler instead of the user code.

I thought about checking the instruction at program counter before single step, remembering
the next pc or possible branch pc and continuing single stepping in debug handler until one of
those is matched. But that would reduce execution speed by at least a factor of 10.

Has anyone a better idea?
Cal

Re: How to single step cpu in xtos sdk using icount?

PostPosted: Thu Jun 11, 2015 4:49 pm
by jcmvbkbc
cal wrote:I want to implement better debugger single stepping on the esp8266.
I am able to use the icount/icountlevel registers for that to debug user level tasks at intlevel 0.
My problem is that the intlevel1 handler executes some code at intlevel 0, too.

First thing that comes to my mind: interrupt handling code needs to turn single-stepping off before lowering intlevel.
Not sure it's possible through standard xtos mechanisms, but at least gdbserver can intercept exception vectors by changing vecbase SR, clear icountlevel, arrange a "call" to the previous handler and restore things after. depc SR may be used as temporary in the level-1 exception handler.

Re: How to single step cpu in xtos sdk using icount?

PostPosted: Thu Jun 11, 2015 11:35 pm
by cal
That sounds like a good idea.
To get access to the debug vector vecbase relocation is already in place.
I will try it.

Thanks,
Cal

Re: How to single step cpu in xtos sdk using icount?

PostPosted: Fri Jun 12, 2015 1:40 am
by cal
jcmvbkbc wrote:depc SR may be used as temporary in the level-1 exception handler.


xtos int1 handler is being jumped to (jx) from vector and being returned from via rte.
So I guess I need depc1/deps1 to get control after the call.
Using other depc feals fishy.
But since the vector has to prepare the interupt framestack anyway I bite a piece of that I and will see If it tastes.
The stack pointer will be already adjusted on rte but the stack frame contents should be still OK I hope.
Hmmmm ... an int2 may come inbetween. So maybe setting deps1 higher may be needed.

Needs some thought.

Cal