- Thu Sep 02, 2021 12:27 am
#92184
I start trying a lot with the nosdk8266 poject, my goal is get the higher frequency possible in the ESP8266, now im fighting with the PLL any have something that can help me in any way?
Moderator: eriksl
- Fri Sep 03, 2021 3:04 am
#92190
Hey guys, i manage to get 379MHz working on my fork https://github.com/0z4/nosdk8266 says 366MHz becouse the max (total max) PLL speed with the locked divider is 183MHz (half 366MHz) but the core runs at 379 
If any know something about the registers to be able to pass that 5.5 divider limit, please post!
If any know something about the registers to be able to pass that 5.5 divider limit, please post!
- Sun Sep 05, 2021 3:43 am
#92198
Great to hear that someone is also interested in getting to know how this works. For some reason the whole clock divider / PLL department of the ESP8266 is very secret and I'd really like to know more.
I can't help you though, I don't know anything about the register layout of the clock divider / PLL, I'd really like to have that documented.
I assume wifi won't work with a CPU clock speed anything other than 80 or 160 MHz, but I think it may be interesting to have the CPU running on higher clocks in small bursts for computationally heavy tasks (like a few hundred milliseconds). Wifi is designed to be able to cope with a client not responding for a few hundred millisecs.
Also I am very interested in what the APB (I/O) bus does. If it always remains at 80 Mhz (probably) not and if not, which peripherals still work.
I can't help you though, I don't know anything about the register layout of the clock divider / PLL, I'd really like to have that documented.
I assume wifi won't work with a CPU clock speed anything other than 80 or 160 MHz, but I think it may be interesting to have the CPU running on higher clocks in small bursts for computationally heavy tasks (like a few hundred milliseconds). Wifi is designed to be able to cope with a client not responding for a few hundred millisecs.
Also I am very interested in what the APB (I/O) bus does. If it always remains at 80 Mhz (probably) not and if not, which peripherals still work.
- Tue Sep 07, 2021 3:35 am
#92223
Currently im mapping all PLL working freq and possible registers. I will share the tables when im ready. This is the code that im using
but i need do it on segments becouse most of what comes out is garbage from an unsupported uart freq, so i need to manual filter all and hand write but i really belive that we can turn off the PLL lock or that at last we can set it to x2 (520MHz) would be impressive see a 40c MCU run at 520MHz!
Code: Select all
uint32_t i = 0x00;
for (i = 0x00; i <= 0xff; i++) {
rom_i2c_writeReg(103, 4, 1, i);
int j = 0;
for (j = 0; j < 200; j++) {
uart_div_modify(0, (j * 1000000) / 115200);
printf("pllworkingreg: 0x%x, pllworkingfreq: %d ", i, j);
}
}
but i need do it on segments becouse most of what comes out is garbage from an unsupported uart freq, so i need to manual filter all and hand write but i really belive that we can turn off the PLL lock or that at last we can set it to x2 (520MHz) would be impressive see a 40c MCU run at 520MHz!
