- Tue Dec 01, 2020 3:09 pm
#89668
There's no corresponding I2STXEOF_NUM so I do think it's Rx specific, and I think what's happening is that datalen tells the DMA subsystem the size of the supplied buffer so that it knows when it's full and can send an interrupt/flip to next, but EOF_NUM tells the FIFO when to trigger a DMA transfer.
the FIFO is 128 words in size, but your supplied DMA buffer can be any size in theory, so I would assume that:
datalen >= I2SRXEOF_NUM <= FIFO max
and datalen would also need to be a multiple of I2SRXEOF_NUM. Right now I have them all set to 128, but potentially if this was the case you could set datalen to 256 or 512 and that would decrease the interrupt frequency. Conversely you could also set datalen and I2SRXEOF_NUM to, say, 64 to get the data more frequently.
I don't see a point in setting I2SRXEOF_NUM less than the max FIFO size without also setting datalen to be the same
the FIFO is 128 words in size, but your supplied DMA buffer can be any size in theory, so I would assume that:
datalen >= I2SRXEOF_NUM <= FIFO max
and datalen would also need to be a multiple of I2SRXEOF_NUM. Right now I have them all set to 128, but potentially if this was the case you could set datalen to 256 or 512 and that would decrease the interrupt frequency. Conversely you could also set datalen and I2SRXEOF_NUM to, say, 64 to get the data more frequently.
I don't see a point in setting I2SRXEOF_NUM less than the max FIFO size without also setting datalen to be the same
