ESP8266 Community Forum

- Fri Nov 27, 2020 10:54 am #89591 I have added in a word length select field into the advanced section. This is the raw value which goes into the I2SC register field. A value of 0 gives 16, and 15 does give 31 bits per word as suspected.

This is with 15

15.jpg

The ESP32 has a very different register set controlling the I2S. In particular it has separate fields for tx and rx word length and they can take values 0-63

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- Fri Nov 27, 2020 8:31 pm #89595 Thank you so much for the scope reading - that's awesome, and damn that really sucks...

I'm going to have to write to Invensense and find out more about the effect of the WS flipping early on the mic. I know I am getting something vaguely sensible because I'm calculating dB and other sound level figures and it is giving back meaningful data.

So this means you can now answer another question - is the bit clock rate affected at all by the word length? Or is it only the word clock that is affected?

For I2S input on these mics, the audio sample rate is driven by the bit clock, so that would mean using 32 as the word length value is actually the right thing to do and 4 + 13 is actually the right choice. Then the only thing to determine is what effect the early flipping of the WS has on the received values

This is awesome research you're doing - very grateful for this insight. This def needs to be moved to the advanced section!!

- Sat Nov 28, 2020 4:37 am #89598 Bit clock is set purely by the two dividers. The I2S_BITS_MOD field then sets the word length when the word select toggles the word signal. It has no effect on the bit clock.

I was surprised that one didn't seem to be able to get a 32 bit word length. I have been looking around the other registers to see if there is anything else that could effect this but no luck so far.

Normally a I2S device is supposed to obey the word select. The invensen doc seems to suggest not, but it could be misleading. At the ESP8266 end it is the word select timing that determines the sample rate so that is the bit that should be close to 48KHz. The proof will come with looking at captured data as a mismatch should give very anomalous results.

I am happy for this topic to be moved.

- Sun Nov 29, 2020 5:26 pm #89630 As has been mentioned in another thread there is also the interesting field called I2S_I2S_TX_DATA_NUM in the FIFO control register which can take values from 0 - 63.

I don't do anything with this at the moment and its purpose doesn't seem to be known or if it is relevant in dma mode. I'll try a few experiments to see if I can figure out what effect it has.