- Mon Jul 06, 2020 3:12 am
#87783
I am using the HSPI peripheral in master mode to transfer data to another device. I want to use a clock rate of 26.67MHz (i.e. 80MHz divided by 3). The other device can handle that speed, however the delay from SCLK to outputting its data on MISO can be up to 15ns.
The problem I have is that when programming the SPI_CLOCK register to divide the system clock by 3, I can only get it to output clock high for 12.5ns and low for 25ns. I am using SPI mode 1 so data is changed on the leading edge and clocked ni on the trailing edge. To handle the 15ns delay, I need the clock to be the other way round, i.e. high for 25ns and low for 12.5ns.
I have read https://www.espressif.com/sites/default ... nce_en.pdf but it doesn't provide alternative ways of setting up a division factor of 3.
I have tried various settings of the SPI1CLK register:
SPI1CLK = (2 << 12) | (2 << 6) | 2; // fails, clock remains high
SPI1CLK = (2 << 12) | (2 << 6) | 1; // fails, clock goes HLHLL
SPI1CLK = (2 << 12) | (2 << 6) | 0; // 12.5ns high, 25ns low
SPI1CLK = (2 << 12) | (1 << 6) | 2; // 12.5ns high, 25ns low
SPI1CLK = (2 << 12) | (1 << 6) | 1; // fails, clock is 80MHz
SPI1CLK = (2 << 12) | (1 << 6) | 0; // fails, clock goes HLHLL
SPI1CLK = (2 << 12) | (0 << 6) | 2; // fails, clock goes HLHLL
SPI1CLK = (2 << 12) | (0 << 6) | 1; // 12.5ns high, 25ns low
SPI1CLK = (2 << 12) | (0 << 6) | 0; // fails, clock is 80MHz
Have I missed anything?
I thought I could get round this by switching to SPI mode 0 so that data is changed on the trailing edge and clocked on the rising edge. But when I do that (by clearing bits 6 and 7 of register SPI_USER instead of setting them), the clock changes to 25ns high and 12.5ns low, which defeats the purpose of changing to mode 1.
Also, can anyone tell me what bit 7 of SPI_USER does? It's not documented in the technical reference, but the driver sets is (along with bit 6) when mode 1 is selected.
The problem I have is that when programming the SPI_CLOCK register to divide the system clock by 3, I can only get it to output clock high for 12.5ns and low for 25ns. I am using SPI mode 1 so data is changed on the leading edge and clocked ni on the trailing edge. To handle the 15ns delay, I need the clock to be the other way round, i.e. high for 25ns and low for 12.5ns.
I have read https://www.espressif.com/sites/default ... nce_en.pdf but it doesn't provide alternative ways of setting up a division factor of 3.
I have tried various settings of the SPI1CLK register:
SPI1CLK = (2 << 12) | (2 << 6) | 2; // fails, clock remains high
SPI1CLK = (2 << 12) | (2 << 6) | 1; // fails, clock goes HLHLL
SPI1CLK = (2 << 12) | (2 << 6) | 0; // 12.5ns high, 25ns low
SPI1CLK = (2 << 12) | (1 << 6) | 2; // 12.5ns high, 25ns low
SPI1CLK = (2 << 12) | (1 << 6) | 1; // fails, clock is 80MHz
SPI1CLK = (2 << 12) | (1 << 6) | 0; // fails, clock goes HLHLL
SPI1CLK = (2 << 12) | (0 << 6) | 2; // fails, clock goes HLHLL
SPI1CLK = (2 << 12) | (0 << 6) | 1; // 12.5ns high, 25ns low
SPI1CLK = (2 << 12) | (0 << 6) | 0; // fails, clock is 80MHz
Have I missed anything?
I thought I could get round this by switching to SPI mode 0 so that data is changed on the trailing edge and clocked on the rising edge. But when I do that (by clearing bits 6 and 7 of register SPI_USER instead of setting them), the clock changes to 25ns high and 12.5ns low, which defeats the purpose of changing to mode 1.
Also, can anyone tell me what bit 7 of SPI_USER does? It's not documented in the technical reference, but the driver sets is (along with bit 6) when mode 1 is selected.
