- Sun Oct 09, 2016 12:40 pm
#56283
Thanks to those who answered. Knowing that someone else had taken the time to look at my problem motivated me to try harder. The problem is now solved. Here is the solution:
1. I installed a large (22mfd) tantalum capacitor between the Vcc and Grd pins of the ESP12e. This reduced the random triggers by 90%. This despite the fact that my power supply module has a 220mfd capacitor directly across its output. When the gurus tell you that you should do that, don't second guess them, believe them;
2. I reduced the value of the pull-up resistor on GPIO0/S3 to 2.2K. This removed the rest of the random triggers. The system is under test and has been solid for 2 days.
I did install a pull-up resistor on /RST but this did not make any difference. I did not get around to installing a small cap on GPIO0. Since the only cost of lowering the value of the pull-up on GPIO0 was increased current consumption when S3 was depressed which is rare and short duration, I felt that it was not worth adding an extra part.
So this topic is now closed by a happy designer
Yves
Yves
