ESP8266 Community Forum

- Thu Mar 29, 2018 11:28 am #74983 Auto reset does work, but it needs the following:
1. schottky between GPIO0 and DTR, cathode to DTR
2. pull-up 10k from GPIO0 to 3.3V
3. ceramic cap 100nF between DTR and CH_PD
4. schottky between CH_PD and 3.3V, cathode to 3.3V
5. pull-up 10k between RESET and 3.3V
6. pull-up 10k between CH_PD and 3.3V
So far this is all to be found on several other blogs, websites and fora. It works well for me as long as I have scope probes attached to GPIO0 and to CH_PD. As soon as I work without scope attached: not working!
So, I decided some parasitic capacitance f****s-up this nice circuit.
SOLUTION:
7. ceramic cap +/-330pF between GPIO0 and GND (ground).
Now it always does do auto-reset when uploading code to the ESP8266 (note: I use the 12f version). I manage to upload code time and time again, without ever having to disconnect power.

It is never too late to learn

- Fri Mar 30, 2018 6:44 am #75010 The reason why reset can't be used is that the modules tend to have a delay capacitor on the reset line which the external capacitor pulse on DTR can't overcome. EN can be successfully used as an alternate reset pin and offers some advantages.

I haven't found an issue with parasitic capacitance but I use a slightly modified scheme with an extra capacitor so the GPIO returns high after the initial boot mode has been read., as attached. The diodes here act as catches to prevent the overvolt when DTR returns high.

The EN pin should be very close to Vdd (3.3V). Mine reads exactly the same. So I would be suspicious of that. The difference sounds a bit like a diode drop but there is nothing in the circuit that would cause that.

I'd take a careful look at the board layout to make sure the connections are as you think. Maybe remove other components e.g. the capacitor leaving just the pull up to EN to see what could be pulling that down.

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