Here is the backstory. I'm looking into using an SGTL5000 for an audio project because it looks like it supports both stereo line in and line out. But the chip wants an extra master clock that is much higher than the bit clock already generated on the I2S interface. I'm trying to see what I can do in software before looking for other options or scrapping this design altogether.
Here is the backstory. I'm looking into using an SGTL5000 for an audio project because it looks like it supports both stereo line in and line out. But the chip wants an extra master clock that is much higher than the bit clock already generated on the I2S interface. I'm trying to see what I can do in software before looking for other options or scrapping this design altogether.