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By zeroday
#5489
zeroday wrote:
sej7278 wrote:
alonewolfx2 wrote:thank you for answers. i tried your bin files and compiled bin files from source code. i saw some differences. firstly your precompiled bin files say 18k heap when first start and source compiled bin files says 14-16k heap. secondly compiled bin files working and booting but restarting when i send same lua files.(ex:dns.lua) what am i missing?


i'm getting the same bootloop issues with my compiled bins when i use file() calls. seems what's in git is maybe not 100% of what we need, or zeroday has made some local changes and forgotten about them.


I compile firmware in win-xp virtual machine. it has 2k ram more than the result from lubuntu.( the reason I stick to winxp vm. much slower though)
I have diff-ed the original win-xp virtual machine and the one I use now. (C:\usr\xtensa\XtDevTools\install), nothing found.
for the lubuntu toolchain, I do remember that I copy two header files from winxp, to get compile through. forget which file...



two files are: simcall-errno.h and simcall-fcntl.h from winxp VM.
these two files get me compile the code without error in lubuntu.
never run firmware compiled from lubuntu before this morning.
and, I get this reboot loop issue too with the firmware compile from lubuntu...
don't know why yet...
User avatar
By alonewolfx2
#5502 I am waiting for solution :) i enabled debug mode and i am getting this error after file.write operation

Code: Select allFatal exception (9):
epc1=0x4022fcb5, epc2=0x00000000, epc3=0x00000000, excvaddr=0x3ffef43f, depc=0x00000000
User avatar
By sej7278
#5513
zeroday wrote:two files are: simcall-errno.h and simcall-fcntl.h from winxp VM.
these two files get me compile the code without error in lubuntu.
never run firmware compiled from lubuntu before this morning.
and, I get this reboot loop issue too with the firmware compile from lubuntu...
don't know why yet...


could you post those two files please, i'm downloading the 2 vm's but baidu.com is the slowest website on earth it seems and has another 9 hours to go (been running for 6!) although i don't seem to have a problem with them anymore, i definitely was, maybe i commented out the #includes somewhere!

what kind of size bin files are you getting - nowhere near 512k are they?

here's the tail end of my build which doesn't seem right regarding size/padding etc......

Code: Select all+ rm ../bin/eagle.app.v6.flash.bin ../bin/eagle.app.v6.irom0text.bin ../bin/eagle.app.v6.dump ../bin/eagle.app.v6.S
+ cd .output/eagle/debug/image
+ xt-objdump -x -s eagle.app.v6.out
+ xt-objdump -S eagle.app.v6.out
+ xt-objcopy --only-section .text -O binary eagle.app.v6.out eagle.app.v6.text.bin
+ xt-objcopy --only-section .data -O binary eagle.app.v6.out eagle.app.v6.data.bin
+ xt-objcopy --only-section .rodata -O binary eagle.app.v6.out eagle.app.v6.rodata.bin
+ xt-objcopy --only-section .irom0.text -O binary eagle.app.v6.out eagle.app.v6.irom0text.bin
+ ../../../../../tools/gen_appbin.py eagle.app.v6.out v6
40100004
3ffe8000
3ffe8bc0
genflashbinv6 eagle.app.v6.text.bin 40100004 eagle.app.v6.data.bin 3ffe8000 eagle.app.v6.rodata.bin 3ffe8bc0
text start_addr 0x40100004
data start_addr 0x3ffe8000
rodata start_addr 0x3ffe8bc0
ERROR: text seg len is 7102 is NOT 4-byte aligned!! Need to pad
text size7104
data sizebc0
rodata size5174
header size is 8 block header size 18 total size is ce59 pad is 0x7 blocks 
chksum text ba
chksum data cc
chksum all ac
text load_addr 0x40100000 len 0x7104
data load_addr 0x3ffe8000 len 0xbc0
rodata load_addr 0x3ffe8bc0 len 0x5174