if that doesn't help, determination is the way forward: seperate tests. Test the modules one by one and try to find which upper/lower speed it reliably works. Then combine two of them and try the same. This should help you determine a) the best speed for all modules and b) the culprit that is picky about busstates and timing...
There are documents about i2c bus that suggest to "clear" the bus befor the master starts a new communication by toggling the clk xx times; worth a try.