I wonder under such arrangement how can I write an ISR for example UART RX handler?
Any help will be appreciated.
BS
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void ICACHE_FLASH_ATTR uart0_init(uart_param_t* param, uart_rx_handler_t rx_handler)
{
portENTER_CRITICAL();
_rx_handler = rx_handler;
PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
WRITE_PERI_REG(UART_CLKDIV(UART0), UART_CLK_FREQ / (param->uart_baud_rate));
WRITE_PERI_REG(UART_CONF0(UART0),
param->uart_parity_mode
|
(param->uart_stop_bit << UART_STOP_BIT_NUM_S)
|
(param->uart_xfer_bit << UART_BIT_NUM_S));
// Clear RX and TX FIFO
SET_PERI_REG_MASK(UART_CONF0(UART0), UART_RXFIFO_RST | UART_TXFIFO_RST);
CLEAR_PERI_REG_MASK(UART_CONF0(UART0), UART_RXFIFO_RST | UART_TXFIFO_RST);
// Clear all interrupt
WRITE_PERI_REG(UART_INT_CLR(UART0), 0x1ff);
_xt_isr_attach(ETS_UART_INUM, _uart0_rx_isr);
// RX interrupt conditions: FIFO full (1 char)
SET_PERI_REG_MASK(UART_CONF1(UART0), ((0x01 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S));
// Enable RX Interrupt
SET_PERI_REG_MASK(UART_INT_ENA(UART0), UART_RXFIFO_FULL_INT_ENA | UART_FRM_ERR_INT_ENA);
_xt_isr_unmask(1 << ETS_UART_INUM); // ETS_UART_INTR_ENABLE();
portEXIT_CRITICAL();
}
_xt_isr_attach(ETS_UART_INUM, _uart0_rx_isr);
_xt_isr_unmask(1 << ETS_UART_INUM);
LOCAL uart_rx_handler_t _rx_handler = 0;
LOCAL void _uart0_rx_isr(void)
{
char ch;
// Frame error, ignore and continue
if (UART_FRM_ERR_INT_ST == (READ_PERI_REG(UART_INT_ST(UART0)) & UART_FRM_ERR_INT_ST))
{
// printf("FRM_ERR\r\n");
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_FRM_ERR_INT_CLR);
}
// RX FIFO FULL
else if (UART_RXFIFO_FULL_INT_ST == (READ_PERI_REG(UART_INT_ST(UART0)) & UART_RXFIFO_FULL_INT_ST))
{
//os_printf("RX_FULL\r\n");
while (READ_PERI_REG(UART_STATUS(UART0)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S))
{
ch = READ_PERI_REG(UART_FIFO(UART0)) & 0xFF;
if (_rx_handler)
_rx_handler(ch);
}
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR);
}
}
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