- Sun Oct 11, 2015 8:50 am
#31093
Thanks for your input - I was originally only going to have a cap on the ESP, but what you mentioned made me read up on decoupling. I now have ceramic 1uf capacitors at all of the spots you mentioned
. I must have taken that screenshot after moving some pins, as I can't see how all of those traces could have gone unnoticed as I was designing the board. My labels were definitely on the wrong layer, so I fixed that as well. Here's the latest revision: 
I'm not exactly sure why that yellow line between the top capacitor and the ESP's ground is still showing up - I'm currently investigating that. The DRC clears.
Your post was incredibly helpful - thanks again.
lethe wrote:I didn't read your website, but that PCB layout does not look like it would work. At first glance, there are several issues:
1) you are routing traces straight through the pads for the pin headers.
2) some traces look like they do not have enough clearance to other traces/vias/pads (run a DRC check in eagle).
3) there are no capacitors on that board?! I assume that SMD package near the bottom is a LDO, you should add caps for both the input and output (see datasheet for type & min. values). You should add decoupling caps (ceramic, usually around 100nF, as close to the power pins as possible) for the ESP and the DIP package (some MCU or port expander I assume?).
4) your pin labels appear to be in the top copper layer. If your board will have a soldermask, they'll be readable under the mask (and probably unreadable). Either convert them to silkscreen or add a stopp mask around them.
Thanks for your input - I was originally only going to have a cap on the ESP, but what you mentioned made me read up on decoupling. I now have ceramic 1uf capacitors at all of the spots you mentioned
. I must have taken that screenshot after moving some pins, as I can't see how all of those traces could have gone unnoticed as I was designing the board. My labels were definitely on the wrong layer, so I fixed that as well. Here's the latest revision: I'm not exactly sure why that yellow line between the top capacitor and the ESP's ground is still showing up - I'm currently investigating that. The DRC clears.
Your post was incredibly helpful - thanks again.
