ESP8266 Community Forum

- Tue Nov 17, 2015 1:47 am #34273 Hi all
(RTOS SDK)
i trying to using spiffs to store a html file for http server.

but i don't know what the parameter mean and what vaule should be config?

I am follow the github：https://github.com/pellepl/spiffs/blob/master/docs/TECH_SPEC

but there are so many thing confused me ；

1. why does the block size have two type ：16KB and 64KB？
2. how does the SPIFFS_PHYS_ADDR doing the offset？ is that related eagle.app.v6.ld file setting？ i don't know where is spiffs begin and where is it end ，when i give a vaule of this parameter
3. does the logic block should be only as 128KB？
4. as the spech noting ram buff size should be two times of logic block， why does the test code showing us like that “#define CACHE_BUF_SIZE (LOG_PAGE + 32)*8 ” what is that mean？ should we set “#define CACHE_BUF_SIZE (LOG_PAGE)*2”？？？
why does add 32*8 ？？？

BR

- Tue Nov 17, 2015 2:47 am #34276 hi when i config spiffs as like below :

// total emulated spi flash size
#define PHYS_FLASH_SIZE (1*1024*1024) //1MB
// spiffs file system size
#define SPIFFS_FLASH_SIZE (512*1024) //512 KB
// spiffs file system offset in emulated spi flash
#define SPIFFS_PHYS_ADDR (512*1024) //512KB

#define SECTOR_SIZE 65536 //64KB
#define PHYS_ERASE_BLOCK (SECTOR_SIZE/4) //16KB
#define LOG_BLOCK (SECTOR_SIZE*2) //128KB
#define LOG_PAGE (SECTOR_SIZE/256) //256 byte


#define FD_BUF_SIZE 64*6
#define CACHE_BUF_SIZE (LOG_PAGE + 32)*8



my hardware is ESP01 (1MB) and eagle.app.v6.ld is like below:

Code: Select allMEMORY
{
  dport0_0_seg :                         org = 0x3FF00000, len = 0x10
  dram0_0_seg :                          org = 0x3FFE8000, len = 0x18000
  iram1_0_seg :                          org = 0x40100000, len = 0x8000
  irom0_0_seg :                          org = 0x40210000, len = 0x70000
}


when download and start the device , it always shows me a error~~~~ and reboot again and again !!!!

dhcp server start:(ip:192.168.123.1,mask:255.255.255.0,gw:192.168.123.1)
add if1
bcn 100
spi_flash_read failed: 1 (525308, 8)
spi_flash_read failed: 1 (656380, 8)
spi_flash_read failed: 1 (787452, 8)
spi_flash_read failed: 1 (918524, 8)
TinyDns open socket
spi_flash_read failed: 1 (1049596, 8)
spi_flash_read failed: 1 (1180668, 8)
spi_flash_read failed: 1 (1311740, 8)
TinyDns Bind socket
spi_flash_read failed: 1 (1442812, 8)
spi_flash_read failed: 1 (524288, 260)
spiffs config succes
"Spiffs"(stack_size = 4,task handle = 3fff3848) overflow the heap_size.
"Spiffs"(stack_size = 4,task handle = 3fff3848) overflow the heap_size.
"Spiffs"(stack_size = 4,task handle = 3fff3848) overflow the heap_size.
"Spiffs"(stack_size = 4,task handle = 3fff3848) overflow the heap_size.

- Tue Nov 17, 2015 6:04 am #34287 as the tech_spec noting :
The boundary of a logical block must coincide with one or more physical blocks.

is that mean log_block_size should be 64KB *times？？？
（we discuss w25xXX， don‘t care other flash IC）


The sizes for logical blocks and logical pages always remain the same, they are uniform

what does “remain the same” meaning？
is that mean logic blocks size is same with logic page size？

but as the test code showing，it seems that one logic block include several logic pages？


anyway， how could i config the offset vaule？？？