- Wed Aug 17, 2016 4:19 pm
#53176
Regarding "reset halt": I have found the following:
(Xtensa System Designer’s Guide found on some chinese website)
So there is a port named OCDHaltOnReset and we don't know if it's connected in the RTL anywhere
An ultra-low-power configuration may not have a PIF, but still require some method of
initializing the local memories. One method of initializing a processor would be to have a
master processor program the ultra-low-power processor’s local memories through the
OCD interface. This method involves very few wires to initialize a processor’s memories.
Figure 51 shows a system with a master processor and a slave processor. The master
asserts the OCDHaltOnReset port of the slave processor, before the slave processor
comes out reset. Once the reset is removed, the slave processor enters inter OCD
mode and await instructions from the OCD port, which is driven by a IEEE-compliant
TAP controller. The master processor controls the slave processor TAP through the five
JTAG pins, and issues instructions to write the slave processor’s local memories. The
master can use TIE export states to control the slave, or traditional memory mapped
GPIO as well.
(Xtensa System Designer’s Guide found on some chinese website)
So there is a port named OCDHaltOnReset and we don't know if it's connected in the RTL anywhere
