ESP8266 Community Forum

- Fri Dec 25, 2015 12:24 pm #37111

1 in the rsil instruction is the maximal level of normal interrupts for our lx106 core.

I could be wrong but I believe that non-maskable interrupts can still occur. There has been some work on disabling NMI but I haven't used the technique.

viewtopic.php?f=9&t=3979

Don Kinzer
ZBasic Microcontrollers
http://www.zbasic.net

- Fri Dec 25, 2015 12:33 pm #37112

1 in the rsil instruction is the maximal level of normal interrupts for our lx106 core.

I could be wrong but I believe that non-maskable interrupts can still occur.

You're right.
OTOH AFAIU the issue here was about not letting other parts of user code see inconsistent counters state, and unless that user code could be called from NMI that still can be achieved with regular interrupts disabling.