ESP8266 Community Forum

- Tue Nov 25, 2014 4:00 pm #3307 Is there a proper way to make an atomic section to be 100% sure no interrupt kicks in during it?
is there something like

Code: Select allATOMIC_BLOCK(ATOMIC_RESTORESTATE)
{
...
}

we had on avr or spin_lock_irqsave/spin_unlock_irqrestore calls in linux kernel?

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- Wed Nov 26, 2014 4:20 am #3317

Is there a proper way to make an atomic section to be 100% sure no interrupt kicks in during it?

Code: Select allstatic inline unsigned long arch_local_irq_save(void)
{
        unsigned long flags;
        asm volatile("rsil %0, 1"
                     : "=a" (flags) :: "memory");
        return flags;
}

static inline void arch_local_irq_restore(unsigned long flags)
{
        asm volatile("wsr %0, ps; rsync"
                     :: "a" (flags) : "memory");
}


1 in the rsil instruction is the maximal level of normal interrupts for our lx106 core.
linux mainline has support for xtensa, so you can look up there.

- Wed Nov 26, 2014 5:44 am #3319 Thanks a lot!

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- Thu Dec 24, 2015 10:54 am #37056 I'm in a situation where I think atomic operations are required:

Code: Select allstatic volatile uint16_t counter = 0;

void interruptRoutine()
{ 
  counter++;
}

void setup(void)
{
  attachInterrupt(5, interruptRoutine, FALLING);
}

void loop(void)
{
  static uint16_t counterTemp = 0;
  static uint16_t callCounter = 0;
 
  if(callCounter++ == 10)
  {
    callCounter = 0;
    // These two lines should probably be atomic
    powerCounterTemp = powerCounter;
    powerCounter = 0;

    // Do something with powerCounterTemp...
  }
}

There's no way to know when the interrupt routine is called, it could certainly be between powerCounterTemp = powerCounter; and powerCounter = 0;, which would make some counts miss and that cannot be allowed. How would one go and make sure the 2 lines on the ESP? I really like the ATOMIC_BLOCK way of doing it, but is it available on the ESP?