- Mon May 25, 2015 12:55 pm
#18423
That's what I thought but since the "datasheet" has section 3.4 dedicated to I2C and even "defining" 2 pins to use I thought maybe it did. But re-reading this section I find the following statement:
Both I2C-Master and I2C-Slave are supported. I2C interface functionality can be realized via software programming, the clock frequency can be up to around 100KHz at most. It should be noted that I2C clock frequency should be higher than the slowest clock frequency of the slave device.
So there's no way that a hardware implementation would only support less than 100kHz. But now that bothers me a bit because with a 80MHz CPU clock why would you be limited to "100kHz at most"?
To be honest, it seems to me that there is a lot of "marketing" type information entered into what should be a techincal document.