ESP8266 Community Forum

- Fri Jun 12, 2015 7:26 pm #20305

depc SR may be used as temporary in the level-1 exception handler.

xtos int1 handler is being jumped to (jx) from vector and being returned from via rte.
So I guess I need depc1/deps1 to get control after the call.

epc1, yes. There's no ps save register for level 1 (as we only get here from intlevel 0, and the rest of the ps is left unchanged). But at the entry to the vector you'd need a place to save at least one register, and excsave1 (normally used for that) may be reserved by the original vector handler, that's why I'm talking about the depc.

Hmmmm ... an int2 may come inbetween. So maybe setting deps1 higher may be needed.

It may not, level 2 is the debug level in lx106, only level 3 (NMI), but that shouldn't lower intlevel.

- Sat Jun 13, 2015 1:36 am #20314 I gave it a first try yesterday and just hardcoded icount* instead of saving them.
But I still have to find a way to save original depc1 to be able to return to that after int 1 call.
I can't use depc2 because watchpoints may trigger debug vector.
Nmi are out of control so depc3 is not usable.
As a first shot i used excsave1 to have something to try out.
Single stepping user code worked! Cool.
I thought about using just some plain memory location but I think a constant size save area may
not work at all or needs very careful usage.
I fear int1 calls can stack. While handling some int1 in handler another one may be triggered and enter the handler
to be integrated in the virtual int handling? Needs a closer look.
If thats possible the stacked call would have icount* already disabled so no need to wrap int1 handler and no need
to save original depc1. So a single memory location seems to be enough.

Funny

Cal

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