ESP8266 Community Forum

- Sat Sep 06, 2014 5:36 pm #259 I am beginning to believe the chip looks like this...
Small ROM that can boot from first flash sector
96KB of RAM

At power on first 4KB of flash is loaded and executed.
That sector them loads the next 64KB into the RAM.
Next 172KB of flash is pseudo ROM.
Page faults are used to bring it into the 4KB page buffers (32KB of buffers)
Next 16KB of flash is user params

Then that 256KB image is duplicated to support OTA update.

They support both 4KB and 16KB page sizes so for a 16KB flash there would be two pages instead of eight.

Did they build the MMU option into this CPU?

It would be confusing when the flash image is generated since we don't know the address the pseudo 'ROM' is being faulted into.

Where I get my modules

- Sat Sep 06, 2014 5:50 pm #260

Did they build the MMU option into this CPU?

According to the configuration documentation: yes, albeit a very simple one that only provides region protection and no translation. By the way: regions are always 1/8th of the total address space, equally distributed. That does explain why it comes into action when some code that apparently gets run accesses 0x006102fc.

- Sat Sep 06, 2014 5:53 pm #261 Header file says full MMU, but I know nothing about Xtensa MMUs

# define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */

Where I get my modules

- Sat Sep 06, 2014 5:55 pm #262 That may be true, the configuration summary is not particulary explicit with statements like "MMU: Region Protection"

Edit: after reading some more documentation, I am sure "MMU: Region Protection" and the define you mentioned are contradictive.