ESP8266 Community Forum

- Sat Sep 06, 2014 6:03 pm #265 Check other thread here:
viewtopic.php?f=6&t=39&p=263#p257

- Sat Sep 06, 2014 6:08 pm #266 Random email about QEMU...
osdir.com /ml/qemu-devel/2012-01/msg01395.html

It has a TLB when that flag is set.

+#if XCHAL_HAVE_PTP_MMU
+
#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
.nways = ways, \
.way_size = { \
@@ -268,11 +270,23 @@
#define DTLB(varway56) \
TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)

Where I get my modules

- Sat Sep 06, 2014 6:10 pm #267 If you are a total hardcore... take that flash image and stick it into the Xtensa QEMU and start single stepping. You should be able to see the page faults.

Where I get my modules

- Sat Sep 06, 2014 6:57 pm #271

# define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */

Where in the "header" (what header?) did you find that anyway?

I only find one such line, which is clearly #if 0'd (and hence effectively commented out). In the lx106 overlay config/core.h, I also clearly find

Code: Select all#define XCHAL_HAVE_TLBS         1   /* inverse of HAVE_CACHEATTR */
#define XCHAL_HAVE_SPANNING_WAY      1   /* one way maps I+D 4GB vaddr */
#define XCHAL_SPANNING_WAY      0   /* TLB spanning way number */
#define XCHAL_HAVE_IDENTITY_MAP      1   /* vaddr == paddr always */
#define XCHAL_HAVE_CACHEATTR      0   /* CACHEATTR register present */
#define XCHAL_HAVE_MIMIC_CACHEATTR   1   /* region protection */
#define XCHAL_HAVE_XLT_CACHEATTR   0   /* region prot. w/translation */
#define XCHAL_HAVE_PTP_MMU      0   /* full MMU (with page table
                     [autorefill] and protection)
                     usable for an MMU-based OS */


So: no address translation, no page table autorefill, just region protection.