pvvx wrote:eriksl wrote:What I mean is that you can't really expect NANOsecond operation in software. If only because of several things you cannot predict:
- cache behaviour
- interrupts
- compiler optimisation
Every interrupt can mess up the cache completely, for instance. If that means your code runs from flash instead of sram (cache), that will make a whole lot of difference.
NMI strobe ~38 ns (~6 CLK CPU 160 MHz)
Code IRAM section.
Synchronise fifo bus...
Output i/o pin = 10 ns jitter.
Min step ~100..200 ns. Steps only synchronise I/O bus
PWM and WLAN operation also use NMI...