- Tue Nov 03, 2015 10:59 am
#32942
Looking at the schematics I can find, there is a 26 MHz crystal with a specified accuracy of 15 ppm, which I suspect is required for the frequency reference of the WiFi hardware.
I also assume that this 26 MHz reference is also used to generate the 80 or 160 MHz CPU master clock, although not an even multiple, so some kind of fractional synthesizer is probably involved. Using the real-time-counter, I am measuring a frequency error of about 70 ppm.
So, before I start ripping the module apart and measuring the 26 MHz crystal directly, does anyone have information about, or can point me to documentation as to how the CPU master clock is derived. Are there small errors in frequency inherent in the clock tree, or is the master 26 MHz oscillator likely not meeting specifications?
I would happy if I could get the master CPU running at 15 ppm accuracy, which is about 1.3 seconds per day.
Thanks,
--- Graham
==
I also assume that this 26 MHz reference is also used to generate the 80 or 160 MHz CPU master clock, although not an even multiple, so some kind of fractional synthesizer is probably involved. Using the real-time-counter, I am measuring a frequency error of about 70 ppm.
So, before I start ripping the module apart and measuring the 26 MHz crystal directly, does anyone have information about, or can point me to documentation as to how the CPU master clock is derived. Are there small errors in frequency inherent in the clock tree, or is the master 26 MHz oscillator likely not meeting specifications?
I would happy if I could get the master CPU running at 15 ppm accuracy, which is about 1.3 seconds per day.
Thanks,
--- Graham
==
