ESP8266 Community Forum

- Mon Sep 08, 2014 10:10 pm #372 @jcmvbkbc

I'm fairly experienced at gcc hacking but am having trouble wrapping my mind around this particular xtensa architecture.

I noticed in another topic it was discovered that this chip is lx106 (did I get that right?) so it's not actually using any custom instructions -- it's an "off the shelf" xtensa architecture.

If you have access to or can write a little about the chip architecture and its instruction set, that would help! Especially if you can describe how the chip architecture differs from what gcc currently supports, though I would guess that's something not 100% known at this time.

- Mon Sep 08, 2014 10:50 pm #373

I noticed in another topic it was discovered that this chip is lx106 (did I get that right?) so it's not actually using any custom instructions -- it's an "off the shelf" xtensa architecture.

Yes, according to data from the configuration overlay this processor doesn't have any custom instructions in it. But the name lx106 is not one of the well-known names.

If you have access to or can write a little about the chip architecture and its instruction set, that would help!

I can't find the latest official ISA book on the Cadence site (it used to be accessible at Tensilica site), but google found this one: http://0x04.net/~mwk/doc/xtensa.pdf which is rather recent.

Especially if you can describe how the chip architecture differs from what gcc currently supports, though I would guess that's something not 100% known at this time.

The difference is that there's no windowed registers support in the lx106. It means there are no entry, retw, call8 and callx8 instructions that gcc emits unconditionally (for many other options there are configuration parameters in the include/xtensa-config.h that guide code generation). There are two ABIs for xtensa: windowed register ABI and call0 ABI. Windowed ABI is well documented, but I can't find much about stack layout of the call0 ABI (I'll search for it more). The correct implementation of that ABI is required for interoperation with the object files distributed by Espressif.

- Tue Sep 09, 2014 2:39 am #375 out of curiosity, what is LX106? From the leaked VM config it is "LX3.0.1" hardware architecure, core 106Micro, most features set to "no".

But 106Micro is actually hardware architecture Xtensa 8, released just before LX3 announcement:
http://ip.cadence.com/uploads/pdf/Tensi ... eprint.pdf

And yes, Xtensa 8 have LX3 core (so Xtensa 8 was not based on Xtensa 7 but on LX3 but no FLIX, hmm, the pdf above say somethign else).

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But isn't 106Micro the Diamon 106Micro?



Anyway, i don't know Xtensa, so simply wondering.

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- Tue Sep 09, 2014 3:30 am #376 I think the ESP8266 is a Diamond Standard 106Micro, so yes it is Xtensa 8, but no it is not a full implementation of all the optional features of Xtensa LX3.

The 106Micro is the lowest tier in terms of performance ... probably has very low power usage too.

@jcmvbkbc: thanks for the link to the ISA doc. If there were a wiki here on the site somewhere I would probably post the ISA doc URL and the Diamond 106Micro image, next to the xtensa options file for gcc.