ESP8266 Community Forum

- Tue Dec 16, 2014 4:07 am #4911 I now working ESP8266ex UART. some things confuse me
it's seem the ESP8266 low libs debuger log and bootloader{ROM code loader image from SPI flash and initialize to user_init() or others } use it.
I has some questions:
1) who use the "UartDevice UartDev" ? the only bootloader? or the wifi/tcp&ip stack libs?
could application disable or modify it?
2) where can we find the Pin Maps of UART0/UART1? include CTS/RTS/TxD/RxD.
3) which uart use by bootloader?
4) could we rewrite UART driver? it's provide difference API.


5) why the interrupt ISR did not have ICACHE_FLASH_ATTR attribute? How make sure it always in RAM or ICACHE?

- Tue Dec 16, 2014 5:14 am #4915

5) why the interrupt ISR did not have ICACHE_FLASH_ATTR attribute? How make sure it always in RAM or ICACHE?

Interrupts are supposed to be handled fast and thus should run from the fastest ram available. running from rom would require to load the isr from spi to ram and present a big overhead. using no attribute would locate it into ram

- Tue Dec 16, 2014 7:20 pm #4983 Got! Thank you! Sjaak!

- Wed Dec 17, 2014 5:05 am #5001 we have a unexpected behavior:
when compile in this line code in uart_config().
SET_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA);
the firmware seem dead{it look like stop at after load image from SPI}. not output! no "Start esp_platform_init" output.
void user_init(void)
{
uart_init(BIT_RATE_74880, BIT_RATE_74880);
ESP_DBG("Start esp_platform_init \r\n");
esp_platform_init();
ESP_DBG("system Ready\r\n");
....
}
is ESP8266 always generate interrupt when in TX FIFO empty? even if firmware clear this bit in UART_INT_CLR register.
what's other interrupt? like RX timeout?