Is this mode functional and usable? The sections 6 & 7 mentions some signal lines which I have not been able to figure out.
This protocol uses the ESP8266 slave mode to communicate with other processor's SPI master. Signal line No.5 is used to implement this protocol. Apart from signal line No.4 needed for standard SPI, signal line No.1 is also needed to inform the master of the update of the slave status register.
What are these signal lines mentioned?
I have seen lots of projects using the ESP8266 as a UART-WIFI passthrough device. I was hoping that the SPI passthrough could yield a higher throughput. Is this a correct assumption? I am planning to use an ESP-12E device.
Any insights into this would be greatly appreciated.