What is interesting is the "release power down" is done by "read chip id" instruction. So if ESP boot code issues this read chip id it will effectively wake up the SPI flash.
This needs to be proven with logic analyzer on the SPI bus and the fun can begin...
But still this idle consumption is not a problem - even in most extreme scenarios of rarely waking sensor nodes, the average active of 70-100mA for 2-3 seconds every 30minutes will be higher that the 40-50uA of the chip (or chips).
I suspect that some of those sleep uAs might be caused by floating inputs? Has anybody tried to solve this by setting fixed levels with external weak pull up/down resistors?