ESP8266 Community Forum

- Mon Dec 30, 2019 11:18 am #85099 Thanks again so much for your help.

CSPI can be used with RTOS.

So CSPI is the interface used for flash? And HSPI is the other SPI on GPIO12/13/14/15?

GPIO01 must be high during normal boot

Do you mean GPIO0? Because GPIO1 is U0TX. According to Page 11:

Note:
1. GPIO2, GPIO0, and MTDO are used to select booting mode and the SDIO mode;

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Edit: If GPIO0 is used for boot mode selection and GPIO1 (U0TXD) is used for programming then I don't really see a possibility to connect another device to this SPI if there is no way to use other GPIOs for CS.
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You could map the debug out to a different pin if you wanted to use the other CS for another device.

But programming always has to happen through U0TX/U0RX - right? Or am I wrong with that?

Don't know about using NOR.

Okay, nevermind. I thought all SPI flash is NOR-based

- Mon Dec 30, 2019 5:02 pm #85103 Yes HSPI is the one using 12,13,14,15 and CSPI is the one shared with flash.

Sorry, yes I meant GPIO00 which must be high for normal boot running from flash.

For serial flashing GPIO00 is held low during reset and then code uploaded with the normal TX,RX pins. During that operation the sharing of the CSPI is not being used. When the code then subsequently runs (reset GPIO00 high) then the code could re-assign debug information to come out of a different pin if the TX pin was being used as a SPI CS. It does mean the debug port must be connected differently compared with upload which is slightly inconvenient. I only ever serial upload once onto a fresh chip as I always include OTA for subsequent updates as that is faster and more convenient.

- Mon Dec 30, 2019 5:58 pm #85106 Thank you so much btidey.

I am sorry to ask all this dumb questions but I want to understand so I don't make mistakes in my PCB layout.

It does mean the debug port must be connected differently compared with upload which is slightly inconvenient.

You are right, and because of that inconvenience I am not going to re-assign the debug port to the other UART. That leads me to the question if GPIO0 can be used as CS after the chip was programmed (because we obviously need it to be pulled low to enter programming mode)? Can a high-value pulldown resistor (like 10K) interfere with SPI Chip-select functionality?

- Tue Dec 31, 2019 10:19 am #85116 A pull up resistor of that value is fine and will not affect the CS functionality as the GPIO can easily sink the current from this. GPIO00 actually has a weak pull up (~36k) during boot so it will default to high but many choose to supplement this with an external 10K pull up to make it more positive.